sandpile.org -- x86 architecture -- 2 byte opcodes

x86 architecture
2 byte opcodes

note: A leading bold V indicates that the instruction can be VEX-encoded, in which case it may have additional operands.
note: A leading bold ! indicates that the 256-bit version was only introduced with AVX2 and that it can only be VEX-encoded.

pre- fix	0Fh xxh	x0h	x1h	x2h	x3h	x4h	x5h	x6h	x7h
n/a	0xh	group #6	group #7	LAR Gv,Ew	LSL Gv,Ew	LOADALL? RESET? HANG? (80286)	LOADALL (80286) SYSCALL (see CPUID)	CLTS	LOADALL (80386) SYSRET (see CPUID)
n/a	1xh	UMOV Eb,Gb (80386/486)	UMOV Ev,Gv (80386/486)	UMOV Gb,Eb (80386/486)	UMOV Gv,Ev (80386/486)
n/a		VMOVUPS Vx,Wx (SSE)	VMOVUPS Wx,Vx (SSE)	VMOVLPS Vo,Ho,Mo.q (SSE) VMOVHLPS #1 Vo,Ho,Uo (SSE)	VMOVLPS Mo.q,Vo (SSE)	VUNPCKLPS Vx,Hx,Wx (SSE) ^#3	VUNPCKHPS Vx,Hx,Wx (SSE)	VMOVHPS Vo,Ho,Mo.q (SSE) VMOVLHPS #1 Vo,Ho,Uo (SSE)	VMOVHPS Mo.q,Vo (SSE)
66h		VMOVUPD Vx,Wx (SSE2)	VMOVUPD Wx,Vx (SSE2)	VMOVLPD Vo,Ho,Mo.q (SSE2)	VMOVLPD Mo.q,Vo (SSE2)	VUNPCKLPD Vx,Hx,Wx (SSE2) ^#3	VUNPCKHPD Vx,Hx,Wx (SSE2)	VMOVHPD Vo,Ho,Mo.q (SSE2)	VMOVHPD Mo.q,Vo (SSE2)
F3h		VMOVSS Vo,Mo.d (SSE) VMOVSS Vo,Ho,Uo (SSE)	VMOVSS Mo.d,Vo (SSE) VMOVSS Uo,Ho,Vo (SSE)	VMOVSLDUP Vx,Wx (SSE3)				VMOVSHDUP Vx,Wx (SSE3)
F2h		VMOVSD Vo,Mo.q (SSE2) VMOVSD Vo,Ho,Uo (SSE2)	VMOVSD Mo.q,Vo (SSE2) VMOVSD Uo,Ho,Vo (SSE2)	VMOVDDUP Vo,Wo.q Vy,Wy (SSE3)
n/a	2xh					SSE5A (AMD)	SSE5A (AMD)
n/a		MOV^{#mod, F64} Ry,Cy (80386+)	MOV^{#mod, F64} Ry,Dy (80386+)	MOV^{#mod, F64} Cy,Ry (80386+)	MOV^{#mod, F64} Dy,Ry (80386+)	MOV^{#mod, F64} Ry,Ty (80386/486)		MOV^{#mod, F64} Ty,Ry (80386/486)
F0h		MOV^#mod Rd,CR8D (see CPUID)		MOV^#mod CR8D,Rd (see CPUID)
n/a	3xh	WRMSR (see CPUID)	RDTSC (see CPUID)	RDMSR (see CPUID)	RDPMC (P55 and P6+)	SYSENTER (see CPUID) (LM: Intel-only)	SYSEXIT (see CPUID) (LM: Intel-only)		GETSEC (see CPUID)
n/a	3xh							RDSHR^#reg Ed (Cyrix)	WRSHR^#reg Ed (Cyrix)
n/a	4xh	CMOVO Gv,Ev (see CPUID)	CMOVNO Gv,Ev (see CPUID)	CMOVB Gv,Ev (see CPUID)	CMOVNB Gv,Ev (see CPUID)	CMOVZ Gv,Ev (see CPUID)	CMOVNZ Gv,Ev (see CPUID)	CMOVBE Gv,Ev (see CPUID)	CMOVNBE Gv,Ev (see CPUID)
n/a	5xh	VMOVMSKPS Gy,Ux (SSE)	VSQRTPS Vx,Wx (SSE)	VRSQRTPS Vx,Wx (SSE)	VRCPPS Vx,Wx (SSE)	VANDPS Vx,Hx,Wx (SSE)	VANDNPS Vx,Hx,Wx (SSE)	VORPS Vx,Hx,Wx (SSE)	VXORPS Vx,Hx,Wx (SSE)
66h		VMOVMSKPD Gy,Ux (SSE2)	VSQRTPD Vx,Wx (SSE2)			VANDPD Vx,Hx,Wx (SSE2)	VANDNPD Vx,Hx,Wx (SSE2)	VORPD Vx,Hx,Wx (SSE2)	VXORPD Vx,Hx,Wx (SSE2)
F3h			VSQRTSS Vo,Ho,Wo.d (SSE)	VRSQRTSS Vo,Ho,Wo.d (SSE)	VRCPSS Vo,Ho,Wo.d (SSE)
F2h			VSQRTSD Vo,Ho,Wo.q (SSE2)
n/a	6xh	PUNPCKLBW Pq,Qd (MMX)	PUNPCKLWD Pq,Qd (MMX)	PUNPCKLDQ Pq,Qd (MMX)	PACKSSWB Pq,Qq (MMX)	PCMPGTB Pq,Qq (MMX)	PCMPGTW Pq,Qq (MMX)	PCMPGTD Pq,Qq (MMX)	PACKUSWB Pq,Qq (MMX)
66h	6xh	!VPUNPCKLBW Vx,Hx,Wx (SSE2) ^#3	!VPUNPCKLWD Vx,Hx,Wx (SSE2) ^#3	!VPUNPCKLDQ Vx,Hx,Wx (SSE2) ^#3	!VPACKSSWB Vx,Hx,Wx (SSE2)	!VPCMPGTB Vx,Hx,Wx (SSE2)	!VPCMPGTW Vx,Hx,Wx (SSE2)	!VPCMPGTD Vx,Hx,Wx (SSE2)	!VPACKUSWB Vx,Hx,Wx (SSE2)
n/a	7xh	PSHUFW Pq,Qq,Ib (MMX-SSE)	group #12 PSHIMW (MMX)	group #13 PSHIMD (MMX)	group #14 PSHIMQ (MMX)	PCMPEQB Pq,Qq (MMX)	PCMPEQW Pq,Qq (MMX)	PCMPEQD Pq,Qq (MMX)	EMMS (MMX) VZEROUPPER (0) VZEROALL (L=1) (AVX)
66h		!VPSHUFD Vx,Wx,Ib (SSE2)	group #12 !VPSHIMW (SSE2)	group #13 !VPSHIMD (SSE2)	group #14 !VPSHIMQ/DQ (SSE2)	!VPCMPEQB Vx,Hx,Wx (SSE2)	!VPCMPEQW Vx,Hx,Wx (SSE2)	!VPCMPEQD Vx,Hx,Wx (SSE2)
F3h		!VPSHUFHW Vx,Wx,Ib (SSE2)	group #12	group #13	group #14
F2h		!VPSHUFLW Vx,Wx,Ib (SSE2)	group #12	group #13	group #14
n/a	8xh	JO^Df64 Jz (80386+)	JNO^Df64 Jz (80386+)	JB^Df64 Jz (80386+)	JNB^Df64 Jz (80386+)	JZ^Df64 Jz (80386+)	JNZ^Df64 Jz (80386+)	JBE^Df64 Jz (80386+)	JNBE^Df64 Jz (80386+)
n/a	9xh	SETO^#reg Eb (80386+)	SETNO^#reg Eb (80386+)	SETB^#reg Eb (80386+)	SETNB^#reg Eb (80386+)	SETZ^#reg Eb (80386+)	SETNZ^#reg Eb (80386+)	SETBE^#reg Eb (80386+)	SETNBE^#reg Eb (80386+)
n/a	Axh							XBTS and CMPXCHG (386/486-A)	IBTS and CMPXCHG (386/486-A)
n/a	Axh	PUSH^D64 FS (80386+)	POP^D64 FS (80386+)	CPUID (EFLAGS.ID)	BT Ev,Gv (80386+)	SHLD Ev,Gv,Ib (80386+)	SHLD Ev,Gv,CL (80386+)	MONTMUL (Centaur MM) XSHA (Centaur HE)	XSTORE (Centaur RNG) XCRYPT (Centaur ACE)
n/a	Bxh	CMPXCHG Eb,Gb (80486-B+)	CMPXCHG Ev,Gv (80486-B+)	LSS Gv,Mp (w:v) (80386+)	BTR Ev,Gv (80386+)	LFS Gv,Mp (w:v) (80386+)	LGS Gv,Mp (w:v) (80386+)	MOVZX Gv,Eb (80386+)	MOVZX Gv,Ew (80386+)
n/a	Cxh	XADD Eb,Gb (80486+)	XADD Ev,Gv (80486+)	VCMPccPS ^#2 Vx,Hx,Wx,Ib (SSE)	MOVNTI My,Gy (SSE2-MEM)	PINSRW Pq,Mw,Ib Pq,Rv,Ib (MMX-SSE)	PEXTRW Gy,Nq,Ib (MMX-SSE)	VSHUFPS Vx,Hx,Wx,Ib (SSE)	group #9
66h				VCMPccPD ^#2 Vx,Hx,Wx,Ib (SSE2)		VPINSRW Vo,Ho,Mw,Ib Vo,Ho,Rv,Ib (SSE2)	VPEXTRW Gy,Uo,Ib (SSE2)	VSHUFPD Vx,Hx,Wx,Ib (SSE2)
F3h				VCMPccSS ^#2 Vo,Ho,Wo.d,Ib (SSE)
F2h				VCMPccSD ^#2 Vo,Ho,Wo.q,Ib (SSE2)
n/a	Dxh		PSRLW Pq,Qq (MMX)	PSRLD Pq,Qq (MMX)	PSRLQ Pq,Qq (MMX)	PADDQ Pq,Qq (MMX-SSE2)	PMULLW Pq,Qq (MMX)		PMOVMSKB Gy,Nq (MMX-SSE)
66h		VADDSUBPD Vx,Hx,Wx (SSE3)	!VPSRLW Vx,Hx,Wx (SSE2) ^#4	!VPSRLD Vx,Hx,Wx (SSE2) ^#4	!VPSRLQ Vx,Hx,Wx (SSE2) ^#4	!VPADDQ Vx,Hx,Wx (SSE2)	!VPMULLW Vx,Hx,Wx (SSE2)	VMOVQ Wo.q,Vo (SSE2)	!VPMOVMSKB Gy,Ux (SSE2)
F3h								MOVQ2DQ Vo,Nq (SSE2-MMX)
F2h		VADDSUBPS Vx,Hx,Wx (SSE3)						MOVDQ2Q Pq,Uq (SSE2-MMX)
n/a	Exh	PAVGB Pq,Qq (MMX-SSE)	PSRAW Pq,Qq (MMX)	PSRAD Pq,Qq (MMX)	PAVGW Pq,Qq (MMX-SSE)	PMULHUW Pq,Qq (MMX-SSE)	PMULHW Pq,Qq (MMX)		MOVNTQ Mq,Pq (MMX-SSE)
66h		!VPAVGB Vx,Hx,Wx (SSE2)	!VPSRAW Vx,Hx,Wx (SSE2) ^#4	!VPSRAD Vx,Hx,Wx (SSE2) ^#4	!VPAVGW Vx,Hx,Wx (SSE2)	!VPMULHUW Vx,Hx,Wx (SSE2)	!VPMULHW Vx,Hx,Wx (SSE2)	VCVTTPD2DQ Vo,Wx (SSE2)	VMOVNTDQ Mx,Vx (SSE2)
F3h								VCVTDQ2PD Vo,Wo.q Vy,Wo (SSE2)
F2h								VCVTPD2DQ Vo,Wx (SSE2)
n/a	Fxh		PSLLW Pq,Qq (MMX)	PSLLD Pq,Qq (MMX)	PSLLQ Pq,Qq (MMX)	PMULUDQ Pq,Qq (MMX-SSE2)	PMADDWD Pq,Qq (MMX)	PSADBW Pq,Qq (MMX-SSE)	MASKMOVQ Pq,Nq (MMX-SSE)
66h			!VPSLLW Vx,Hx,Wx (SSE2) ^#4	!VPSLLD Vx,Hx,Wx (SSE2) ^#4	!VPSLLQ Vx,Hx,Wx (SSE2) ^#4	!VPMULUDQ Vx,Hx,Wx (SSE2)	!VPMADDWD Vx,Hx,Wx (SSE2)	!VPSADBW Vx,Hx,Wx (SSE2)	VMASKMOVDQU Vo,Uo (SSE2)
F3h
F2h		VLDDQU Vx,Mx (SSE3)

pre- fix	0Fh xxh	x8h	x9h	xAh	xBh	xCh	xDh	xEh	xFh
n/a	0xh	INVD (80486+)	WBINVD (80486+)		UD1 (80286+)		3DNow!	3DNow!	3DNow!
n/a	1xh	group #16	group #16	group #16	group #16	group #16	group #16	group #16	group #16
n/a	2xh	VMOVAPS Vx,Wx (SSE)	VMOVAPS Wx,Vx (SSE)	(no V) CVTPI2PS Vo,Mq (SSE) CVTPI2PS Vo,Nq (SSE-MMX)	VMOVNTPS Mx,Vx (SSE)	CVTTPS2PI Pq,Wo.q (SSE-MMX)	CVTPS2PI Pq,Wo.q (SSE-MMX)	VUCOMISS Vo,Wo.d (SSE)	VCOMISS Vo,Wo.d (SSE)
66h		VMOVAPD Vx,Wx (SSE2)	VMOVAPD Wx,Vx (SSE2)	(no V) CVTPI2PD Vo,Mq (SSE2) CVTPI2PD Vo,Nq (SSE2-MMX)	VMOVNTPD Mx,Vx (SSE2)	CVTTPD2PI Pq,Wo (SSE2-MMX)	CVTPD2PI Pq,Wo (SSE2-MMX)	VUCOMISD Vo,Wo.q (SSE2)	VCOMISD Vo,Wo.q (SSE2)
F3h				VCVTSI2SS Vo,Ho,Ey (SSE)	MOVNTSS Md,Vo (SSE4A)	VCVTTSS2SI Gy,Wo.d (SSE)	VCVTSS2SI Gy,Wo.d (SSE)
F2h				VCVTSI2SD Vo,Ho,Ey (SSE2)	MOVNTSD Mq,Vo (SSE4A)	VCVTTSD2SI Gy,Wo.q (SSE2)	VCVTSD2SI Gy,Wo.q (SSE2)
n/a	3xh	3 byte opcodes (80286+)
n/a	3xh	SMINT (Cyrix) SMINT (Geode LX)	DMINT (Geode LX)	BB0_RESET (Cyrix GX1) RDM (Geode LX)	BB1_RESET (Cyrix GX1)	CPU_WRITE (Cyrix GX1)	CPU_READ (Cyrix GX1)		ALTINST (Centaur AIS)
n/a	4xh	CMOVS Gv,Ev (see CPUID)	CMOVNS Gv,Ev (see CPUID)	CMOVP Gv,Ev (see CPUID)	CMOVNP Gv,Ev (see CPUID)	CMOVL Gv,Ev (see CPUID)	CMOVNL Gv,Ev (see CPUID)	CMOVLE Gv,Ev (see CPUID)	CMOVNLE Gv,Ev (see CPUID)
n/a	5xh	VADDPS Vx,Hx,Wx (SSE)	VMULPS Vx,Hx,Wx (SSE)	VCVTPS2PD Vo,Wo.q Vy,Wo (SSE2)	VCVTDQ2PS Vx,Wx (SSE2)	VSUBPS Vx,Hx,Wx (SSE)	VMINPS Vx,Hx,Wx (SSE)	VDIVPS Vx,Hx,Wx (SSE)	VMAXPS Vx,Hx,Wx (SSE)
66h		VADDPD Vx,Hx,Wx (SSE2)	VMULPD Vx,Hx,Wx (SSE2)	VCVTPD2PS Vo,Wo Vo,Wy (SSE2)	VCVTPS2DQ Vx,Wx (SSE2)	VSUBPD Vx,Hx,Wx (SSE2)	VMINPD Vx,Hx,Wx (SSE2)	VDIVPD Vx,Hx,Wx (SSE2)	VMAXPD Vx,Hx,Wx (SSE2)
F3h		VADDSS Vo,Ho,Wo.d (SSE)	VMULSS Vo,Ho,Wo.d (SSE)	VCVTSS2SD Vo,Ho,Wo.d (SSE2)	VCVTTPS2DQ Vx,Wx (SSE2)	VSUBSS Vo,Ho,Wo.d (SSE)	VMINSS Vo,Ho,Wo.d (SSE)	VDIVSS Vo,Ho,Wo.d (SSE)	VMAXSS Vo,Ho,Wo.d (SSE)
F2h		VADDSD Vo,Ho,Wo.q (SSE2)	VMULSD Vo,Ho,Wo.q (SSE2)	VCVTSD2SS Vo,Ho,Wo.q (SSE2)		VSUBSD Vo,Ho,Wo.q (SSE2)	VMINSD Vo,Ho,Wo.q (SSE2)	VDIVSD Vo,Ho,Wo.q (SSE2)	VMAXSD Vo,Ho,Wo.q (SSE2)
n/a	6xh	PUNPCKHBW Pq,Qq (MMX)	PUNPCKHWD Pq,Qq (MMX)	PUNPCKHDQ Pq,Qq (MMX)	PACKSSDW Pq,Qq (MMX)			MOVD^Q Pq,Ey (MMX)	MOVQ Pq,Qq (MMX)
66h		!VPUNPCKHBW Vx,Hx,Wx (SSE2)	!VPUNPCKHWD Vx,Hx,Wx (SSE2)	!VPUNPCKHDQ Vx,Hx,Wx (SSE2)	!VPACKSSDW Vx,Hx,Wx (SSE2)	!VPUNPCKL- QDQ Vx,Hx,Wx (SSE2) ^#3	!VPUNPCKH- QDQ Vx,Hx,Wx (SSE2)	VMOVD^Q Vo,Ey (SSE2)	VMOVDQA Vx,Wx (SSE2)
F3h									VMOVDQU Vx,Wx (SSE2)
F2h
n/a	7xh	VMREAD Ey,Gy (see CPUID)	VMWRITE Gy,Ey (see CPUID)	SSE5A (AMD)	SSE5A (AMD)			MOVD^Q Ey,Pq (MMX)	MOVQ Qq,Pq (MMX)
66h		EXTRQ Uo,Ib,Ib (/0) (SSE4A)	EXTRQ Vo,Uo (SSE4A)			VHADDPD Vx,Hx,Wx (SSE3)	VHSUBPD Vx,Hx,Wx (SSE3)	VMOVD^Q Ey,Vo (SSE2)	VMOVDQA Wx,Vx (SSE2)
F3h								VMOVQ Vo,Wo.q (SSE2)	VMOVDQU Wx,Vx (SSE2)
F2h		INSERTQ Vo,Uo,Ib,Ib (SSE4A)	INSERTQ Vo,Uo (SSE4A)			VHADDPS Vx,Hx,Wx (SSE3)	VHSUBPS Vx,Hx,Wx (SSE3)
n/a	8xh	JS^Df64 Jz (80386+)	JNS^Df64 Jz (80386+)	JP^Df64 Jz (80386+)	JNP^Df64 Jz (80386+)	JL^Df64 Jz (80386+)	JNL^Df64 Jz (80386+)	JLE^Df64 Jz (80386+)	JNLE^Df64 Jz (80386+)
n/a	9xh	SETS^#reg Eb (80386+)	SETNS^#reg Eb (80386+)	SETP^#reg Eb (80386+)	SETNP^#reg Eb (80386+)	SETL^#reg Eb (80386+)	SETNL^#reg Eb (80386+)	SETLE^#reg Eb (80386+)	SETNLE^#reg Eb (80386+)
n/a	Axh	PUSH^D64 GS (80386+)	POP^D64 GS (80386+)	RSM (SMM) (80386SL+?)	BTS Ev,Gv (80386+)	SHRD Ev,Gv,Ib (80386+)	SHRD Ev,Gv,CL (80386+)	group #15	IMUL Gv,Ev (80386+)
n/a	Bxh	JMPE Jz (IA-64)	group #10 UD2 (80286+)	group #8 Ev,Ib (80386+)	BTC Ev,Gv (80386+)	BSF Gv,Ev (80386+)	BSR Gv,Ev (80386+)	MOVSX Gv,Eb (80386+)	MOVSX Gv,Ew (80386+)
F3h	Bxh	POPCNT Gv,Ev (see CPUID)				TZCNT Gv,Ev (see CPUID)	LZCNT Gv,Ev (see CPUID)
n/a	Cxh	BSWAP rAX / r8 (80486+)	BSWAP rCX / r9 (80486+)	BSWAP rDX / r10 (80486+)	BSWAP rBX / r11 (80486+)	BSWAP rSP / r12 (80486+)	BSWAP rBP / r13 (80486+)	BSWAP rSI / r14 (80486+)	BSWAP rDI / r15 (80486+)
n/a	Dxh	PSUBUSB Pq,Qq (MMX)	PSUBUSW Pq,Qq (MMX)	PMINUB Pq,Qq (MMX-SSE)	PAND Pq,Qq (MMX)	PADDUSB Pq,Qq (MMX)	PADDUSW Pq,Qq (MMX)	PMAXUB Pq,Qq (MMX-SSE)	PANDN Pq,Qq (MMX)
66h	Dxh	!VPSUBUSB Vx,Hx,Wx (SSE2)	!VPSUBUSW Vx,Hx,Wx (SSE2)	!VPMINUB Vx,Hx,Wx (SSE2)	!VPAND Vx,Hx,Wx (SSE2)	!VPADDUSB Vx,Hx,Wx (SSE2)	!VPADDUSW Vx,Hx,Wx (SSE2)	!VPMAXUB Vx,Hx,Wx (SSE2)	!VPANDN Vx,Hx,Wx (SSE2)
n/a	Exh	PSUBSB Pq,Qq (MMX)	PSUBSW Pq,Qq (MMX)	PMINSW Pq,Qq (MMX-SSE)	POR Pq,Qq (MMX)	PADDSB Pq,Qq (MMX)	PADDSW Pq,Qq (MMX)	PMAXSW Pq,Qq (MMX-SSE)	PXOR Pq,Qq (MMX)
66h	Exh	!VPSUBSB Vx,Hx,Wx (SSE2)	!VPSUBSW Vx,Hx,Wx (SSE2)	!VPMINSW Vx,Hx,Wx (SSE2)	!VPOR Vx,Hx,Wx (SSE2)	!VPADDSB Vx,Hx,Wx (SSE2)	!VPADDSW Vx,Hx,Wx (SSE2)	!VPMAXSW Vx,Hx,Wx (SSE2)	!VPXOR Vx,Hx,Wx (SSE2)
n/a	Fxh	PSUBB Pq,Qq (MMX)	PSUBW Pq,Qq (MMX)	PSUBD Pq,Qq (MMX)	PSUBQ Pq,Qq (MMX-SSE2)	PADDB Pq,Qq (MMX)	PADDW Pq,Qq (MMX)	PADDD Pq,Qq (MMX)	UD (AMD)
66h	Fxh	!VPSUBB Vx,Hx,Wx (SSE2)	!VPSUBW Vx,Hx,Wx (SSE2)	!VPSUBD Vx,Hx,Wx (SSE2)	!VPSUBQ Vx,Hx,Wx (SSE2)	!VPADDB Vx,Hx,Wx (SSE2)	!VPADDW Vx,Hx,Wx (SSE2)	!VPADDD Vx,Hx,Wx (SSE2)	UD (AMD)

notes	descriptions
#1	These opcodes are not supported on pre-B0 step Pentium III processors.
#2	The condition codes are EQ, LT, LE, UNORD, NEQ, NLT, NLE, and ORD. They are encoded as the Ib, using 00...07h. With VEX, there also are: EQ_UQ, NGE, NGT, FALSE, NEQ_OQ, GE, GT, TRUE (08...0Fh), EQ_OS, LT_OQ, LE_OQ, UNORD_S, NEQ_US, NLT_UQ, NLE_UQ, ORD_S (10h...17h), and EQ_US, NGE_UQ, NGT_UQ, FALSE_OS, NEQ_OS, GE_OQ, GT_OQ, TRUE_US (18...1Fh).
#3	Ideally the Vo,Ho,Wo variants would be Vo,Ho,Wo.q because they only use the lower half of the source operand.
#4	Ideally the Vo,Ho,Wo variants would be Vo,Ho,Wo.b because they only use the lowest byte of the source operand.

On Cyrix processors the following SMM-related opcodes can be enabled. Note that the SMINT instruction has been moved, to avoid a collision with one of the MMX instructions. Cyrix introduced the RDSHR and WRSHR instructions at the same time.

0Fh xxh	x8h	x9h	xAh	xBh	xCh	xDh	xEh	xFh
7xh	SVDC M10,Sw	RSDC Sw,M10	SVLDT M10	RSLDT M10	SVTS M10	RSTS M10	SMINT

On Cyrix M2 processors the following extended MMX instructions can be enabled.

0Fh xxh	x0h	x1h	x2h	x3h	x4h	x5h	x6h	x7h
5xh	PAVEB Pq,Qq	PADDSIW Pq,Qq	PMAGW Pq,Qq		PDISTIB Pq,Mq	PSUBSIW Pq,Qq
0Fh xxh	x8h	x9h	xAh	xBh	xCh	xDh	xEh	xFh
5xh	PMVZB Pq,Mq	PMULHRW Pq,Qq	PMVNZB Pq,Mq	PMVLZB Pq,Mq	PMVGEZB Pq,Mq	PMULHRIW Pq,Qq	PMACHRIW Pq,Mq

On selected Centaur processors the following MM-, HE-, RNG-, and ACE-related opcodes can be enabled.

	C0h	C8h	D0h	D8h	E0h	E8h	F0h	F8h
0Fh A6h	MONTMUL (MM)	XSHA1 (HE)	XSHA256 (HE)
0Fh A7h	XSTORE (RNG)	XCRYPT-ECB (ACE)	XCRYPT-CBC (ACE)	XCRYPT-CTR (ACE)	XCRYPT-CFB (ACE)	XCRYPT-OFB (ACE)
note	While the REP prefix (F3h) is optional for the XSTORE instruction, it is mandatory for the other instructions.